Fault simulation and test generation for small delay faults

Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they model only a subset of delay defect behaviors. To solve this problem, a more realistic delay fault model has been developed which models delay faults caused by the combination of spot defects and parametric process variation. According to the new model, a realistic delay fault coverage metric has been developed. Traditional path delay fault coverage metrics result in unrealistically low fault coverage, and the real test quality is not reflected. The new metric uses a statistical approach and the simulation based fault coverage is consistent with silicon data. Fast simulation algorithms are also included in this dissertation. The new metric suggests that testing the K longest paths per gate (KLPG) has high detection probability for small delay faults under process variation. In this dissertation, a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate for both combinational and sequential circuits is presented. Many techniques are used to reduce search space and CPU time significantly. Experimental results show that this methodology is efficient and able to handle circuits with an exponential number of paths, such as ISCAS85 benchmark circuit c6288. The ATPG methodology has been implemented on industrial designs. Speed binning has been done on many devices and silicon data has shown significant benefit of the KLPG test, compared to several traditional delay test approaches

Hardware Software Partitioning of Multifunction Systems

The problem of hardware-software partitioning for systems that are being designed as multifunction systems is addressed. Simulated annealing is known to generate very good solutions for most optimization problems, however the running time of this algorithm can be very high. We apply a modified simulated annealing approach to the partitioning problem resulting in a smaller search space, yet yielding good partitions. We show experimental results that yield better solutions in comparison to the existing multifunction partitioning approaches within acceptable running time

A circuit level fault model for resistive shorts of MOS gate oxide. In: 5th international workshop on microprocessor test and verification

Previous researchers in logic testing focused on shorts in MOS gate oxides that have zero-resistance. However, most shorts are resistive and may cause delay faults. In this paper, we propose a simple and realistic delay fault model for gate oxide shorts. A reasonably accurate method is proposed to compute delay change due to resistive shorts. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. 1